TSMC chips away at the competition with 2nm production set for 2025
of its next-generation N2 2nm node at last year's symposium, including that it would switch to a nanosheet transistor architecture, where several stacked layers of silicon are completely surrounded by the transistor gate material, instead of the current FinFET designs.
The company said it is making"solid progress" in both yield and performance of N2 silicon, and that it is expecting it to deliver a better than 1.15 times improvement in density over the enhanced N3E node that is due to enter mass production this year. It is also projected to offer a 15 percent speed improvement over N3E at the same power, or up to a 30 percent power reduction at the same speed when it goes into production in 2025.
With its 3nm N3 process now in volume production and the enhanced N3E version coming, TSMC detailed more 3nm nodes that it plans to bring into production. This expanded lineup will include N3P, which TSMC claims will offer an extra 5 percent more speed than N3E with the same leakage current, or a 5 to 10 percent power reduction at the same speed, plus a slight increase in density. It is due for production in the second half of 2024.
The N3X node will prioritize performance and maximum clock frequencies for HPC applications, and is expected to add another 5 percent speed to that of N3P, but with the same improved chip density as N3P, and set to enter volume production in 2025.
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