Reducing manual effort and achieving better coverage with AI and formal techniques
Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle.
Formal analysis conclusively determines unreachable coverage targets and removes them from consideration for future simulations. This benefits the overall coverage calculation: - Achieve a left shift in coverage and bug finding by applying test grading and unreachability analysis effectivelyAfter the results of Project B, the verification was eager to try additional techniques to further shift left the verification process. For project C, they experimented with AI-based techniques, starting with the Synopsys VSO.ai Verification Space Optimization solution.
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